1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and, more particularly, to a semiconductor memory device having a cell structure of a twin storage type.
2. Description of the Related Art
In a semiconductor memory device having a twin-storage type cell structure, 1-bit data is stored in a pair of memory cells. One of the memory cells stores an inverted data of the data stored in the other one of the memory cells. For instance, if one of the memory cell stores high-level data, the other one of the memory cells stores low-level data. The pair of memory cells is connected to a pair of bit lines. One of the bit lines is amplified to the high level, while the other one of the bit lines is amplified to the low-level.
The difference in charge accumulated in the two memory cells serves to separate the potentials of the two bit lines, so that a steady data read operation can be performed. For instance, if the potential of the memory cell storing the high-level data is lower than the pre-charge level of the bit line due to electric discharge of the memory cell, the difference between the charges accumulated in the two memory cells separates the two bit lines, so that an accurate data read operation can be performed.
In the above semiconductor memory device of the twin-storage type, a steady and accurate data read operation can be performed. The same control operation as in a conventional semiconductor memory device of a single-storage type, despite the above-mentioned advantages, will result in wastes in terms of the process rate, the power consumption, and the chip area. Accordingly, a control operation that is different from the control operation for the conventional semiconductor memory device of the single-storage type should preferably be performed so as to increase the process rate and to reduce the power consumption and the chip area.